1. Field of the Invention
The present invention generally relates to calibrating a comparator offset of a successive-approximation-register (SAR) analog-to-digital converter (ADC).
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “signal,” “sampling,” “circuit node,” “switch,” “comparator,” “finite-state machine,” “analog-to-digital converter (ADC),” and “digital-to-analog converter (DAC).” Terms and basic concepts like these are understood by those of ordinary skill in the art and thus will not be explained in detail here.
A functional block diagram of a successive-approximation-register (SAR) analog-to-digital converter (ADC) 100 is shown in FIG. 1A. SAR ADC 100 comprises: a sampling network 110 sampling an input voltage VIN and outputting a first voltage V1 in accordance with a sampling signal SAMP; a digital-to-analog converter (DAC) 120 converting an output data DO into a second voltage V2; a summing circuit 130 receiving the first voltage V1 and the second voltage V2 and outputting a summed voltage VX; a comparator 140 receiving the summed voltage VX and outputting a binary decision DX indicating a polarity of the summed voltage VX; and a SAR controller 150 receiving the binary decision DX and outputting the sampling signal SAMP and the output data DO. SAR ADC 100 operates in two phases: a sampling phase and a conversion phase. In the sampling phase, the sampling signal SAMP is asserted, and the input voltage VIN is sampled into the first voltage V1. In the conversion phase, the sampling signal SAMP is de-asserted, and the SAR controller 150 conducts a process of successive approximation to adapt the output data DO to make the second voltage V2 approximately equal to the first voltage V1 in accordance with the binary decision DX. The SAR controller 150 increases a value of the output data DO to raise the second voltage V2 and thus lower the summed voltage VX when the binary decision DX is 1, indicating that the summed voltage VX is too high and needs to be lowered. Otherwise the SAR controller 150 decreases the value of the output data DO to lower the second voltage V2 and thus raise the summed voltage VX. At the end of the process of successive approximation, the summed voltage VX is approximately zero, the second voltage V2 is approximately equal to the first voltage V1, and a final value of the output data DO is a digital representation of the input voltage VIN as a result of the successive approximation.
Ideal transfer characteristics of comparator 140 is shown in FIG. 1B. As shown, DX is 1 when VX is greater than 0. Otherwise, DX is 0. A practical comparator, however, might have an offset. Exemplary transfer characteristics of comparator 140 with a 10 mV offset is shown in FIG. 1C. As shown, DX is 1 when VX is greater than 10 mV; otherwise, DX is 0. In the presence of offset (e.g., 10 mV) of comparator 140, the summed voltage VX is approximately equal to the offset voltage (e.g., 10 mV), instead of zero, at the end of the successive approximation. As a result, the second voltage V2 might not be an accurate approximation to the first voltage V1, and the final value of the output data DO might not be an accurate digital representation of the input voltage VIN. This introduces an error to the analog-to-digital conversion and degrades a performance of SAR ADC 100.
Comparator offset can be calibrated by using an “auto-zero” scheme. An “auto-zero” scheme, however, increases complexity of the comparator.
What is desired is a method for calibrating the comparator offset of SAR ADC without increasing complexity of the comparator.